International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,April 2016,

Topic : Design of Flexible Accelerator Based on Recoding Techniques

Authors:Sambhu P.G || Sreejesh Kumar R

Abstract:DSP accelerators are hardware modules attached to a processor core externally to enhance the performance and functionality of computationally intensive DSP functions. Domain specific hardware architectures forms ideal acceleration in terms of performance and power, but their inflexible data paths lead to increased silicon complexity. In flexible DSP accelerator functional computational unit (FCU) are incorporated to improve performance, reduce energy consumption and to provide flexible data paths. The architecture exploits carry save (CS) arithmetic to enable fast chaining of additive and multiplicative operations. However, the carry save optimization approaches have limited impact on data flow graph (DFG) dominated by multiplications. These limitations are tackled by exploiting CS to modified booth recoding, which consists of three algorithms, signed-bit Full Adders (FAs) and Half Adders (HAs) as building blocks. To validate the design, code can be developed using VHDL and synthesis & simulation will be done in Xilinx ISE Suite 13.2 & Model Sim SE 6.3f respectively..

Keywords: carry Save (CS), Flexible Computational Unit (FCU), and Flexible data path

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DOI: 01.1617/vol3iss4pid176


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
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