[1] Advanced Microcontroller Bus Architecture Specification (1997) [Online]. Available: http://www.arm.com

[2] Chin-Yao Chang, Student Member, IEEE, and KuenJong Lee,“On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions ”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 3, pp. 484-496, March 2014.

[3] Mayank Rai Nigam, Mrs Shivangi Bande, “AXI Interconnect Between Four Master and Four Slave Interfaces”, Int. Jou. of Engg. Res. and Gen. Sci., vol. 2, issue 4, pp. 432-446, June-July 2014.

[4] Jing Guo, Liyi Xiao, Zhigang Mao, and Qiang Zhaoz,“ Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,vol. 22, No. 1, January 2014.

[5] AXI Reference Guide, XILINX, UG761 (v13.4) January 18, 2012.

[6] Technical Reference Manual of PrimeCell AXI Configurable Interconnect (PL300), ARM, Cambridge, U.K., 2010.

[7] K. Lahiri, A. Raghunathan, and G. Lakshminarayana, “The LOTTERYBUS on-chip communication architecture”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 6, pp. 596608, Jun. 2006.

[8] T. S. Cummins, “Method and apparatus for detecting a bus deadlock in an electronic system”, U.S. Patent 6 292 910, Sep. 18, 2001