[1] Basant Kumar Mohanty, Novel Block-Formulation and Area-Delay- Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications, IEEE Transactions On Circuits And SystemsI: regular papers, volume:62,no.1,january 2015.

[2] L. P. Usha, Naveen Kumar G. N, Design and implementation of Pulse- Shaping FIR Interpolation filter using BCSE Algorithm, International Journal of Engineering Research & Technology (IJERT)ISSN: 2278- 0181, volume:4,Issue:05,May-2015.

[3] I. Hatai, I. Chakrabarti, and S. Banerjee, Reconfigurable architecture of RRC FIR interpolator for multi-standard digital up converter, in Proc. IEEE 27th Int. Symp. Parallel Distrib. Processing Workshops PhD Forum, 2013, pp.247251.

[4] R. Mahesh and A. P. Vinod, Reconfigurable low area complexity filter bank architecture based on frequency response masking for nonuniform Channelization in software defined radio, IEEE,Trans.Aerosp. Electron. Syst, volume:47,no.2,pp.12411254,Apr.2011.

[5] R. Mahesh and A. P. Vinod, New reconfigurable architectures for implementing FIR filters with low complexity, IEEE Trans.Comput-Aided Design Integr. Circuits Syst, volume:29,no.2,pp.275-288,Feb.2010.

[6] R. Mahesh and A. P. Vinod, Reconfigurable frequency response masking filters for software radio channelization, IEEE Trans.Circuits Syst.II, Exp.Briefs, volume:55, no.3,pp.274278,Mar.2008.

[7] G. C. Cardarilli, A. D. Re, M. Re, and L. Simone, Optimized QPSK modulator for DVB-S application, in Proc. IEEE Int. Symp. Circuits Syst.(ISCAS), 2006,pp.15711577.

[8] J. Park, W. Jeong, H. Mahmoodi-Meimand, Y. Wang, H. Choo, and K. Roy, Computation sharing programmable FIR filter for low-power and highperformance applications, IEEE Journal Solid State Circuits, volume:39, no.2, pp.348357, Feb.2004.

[9] T. Zhangwen, J. Zhang, and H. Min, A high-speed, programmable, CSD coefficient FIR filter, IEEE Trans.Consum.Electronics, volume: 48, no.4,pp.834837, Nov.2002.

[10] N. Sankarayya, K. Roy, and D. Bhattacharya, Algorithms for lowpower high speed FIR filter realization using differential coefficients, IEEE Trans.CircuitsSyst.II, volume:44,pp.488497, June 1997.

[11] R. I. Hartley, Subexpression sharing in filters using canonic signed digit multipliers, IEEE Trans.Circuits Syst.II, volume:43,no.10,pp.677688,Oct.1996.

[12] M. Potkonjak, M. Srivastava, and A. P. Chandrakasan, Multiple constant multiplications: Efficient and versatile framework and algorithms for exploring common subexpression elimination, IEEE Trans.Computer- Aided Design, volume.15,pp.151165,Feb.1996.