International Journal of Engineering Research in Electronics and Communication Engineering (IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,April 2016,

Topic : A Parallel Area Delay Efficient Interpolation Filter Architecture

Authors:Anusha Ajayan || Rafeekha M J

Abstract:Interpolators are widely used in digital signal processing to increase the sampling rate digitally. A multi-standard Software Defined Radio (SDR) system involves interpolation with different filter coefficients, filter length and up-sampling factors to meet the stringent frequency specification. An SDR receiver consumes huge amount of resource when these interpolators are implemented individually in a hardware circuit. A reconfigurable Finite Impulse Response (FIR) interpolation filter is suitable for a resource and power constrained multi-standard SDR receiver. Now-a-days interpolation filter architecture with a few multipliers or without any multipliers are available. Area complexity, irregular dataflow and low hardware utilization efficiency are the major disadvantages of these architectures. In this work, a new parallel multiplier based reconfigurable structure is derived for interpolation filter. Elimination of redundancy and producing multiple outputs without reconfiguration are the features of this architecture. To validate the design, code can be developed using VHDL in Xilinx ISE Design Suite 13.2 and to be simulated in ModelSim SE 6.3f. The Xilinx synthesized result shows that, this architecture has less area, delay and Area-Delay Product (ADP) compared to the other existing architectures..

Keywords: FIR filters, Interpolation, Software Defined Radio.

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DOI: 01.1617/vol3iss4pid187


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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