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[2] Der-Cheng Huang; Wen-Ben Jone, "A parallel built-in self-diagnostic method for embedded memory arrays," in Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.21, no.4, pp.449- 465, Apr 2002.

[3] Design of Built-in Self-Test Core for SRAM by Reeja J. and Anusree L. S. International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 3 Issue 3, March – 2014.

[4] A Failure Testing System with March C-Algorithm for SingleEvent Upset by Peng Wang, ZhenLi, Chengxiang Jiang, Wei Shao and Qiannan Xue International Journal of Hybrid Information Technology Vol.7, No.2 (2014), pp.95-102.

[5] Design of Improved Built-In-Self-Test Algorithm (8n) for Single Port Memory by Manoj Vishnoi, Arun Kumar, Minakshi Sanadhya International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-5, November 2012.

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[7] Testing of Embedded System Version 2 EE IIT, Kharagpur Lesson 40 Built-In-Self-Test (BIST) for Embedded Systems