International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,May 2016,

Topic : A High Speed Performance and Low Power Consumption Design For VLSI Logic Circuits Using Multi-Threshold Voltage CMOS Technology

Authors:Nisha S Police Patil || Swetha B

Abstract:Due to voltage scaling in CMOS logic circuits, there will be a reduction in threshold voltage which leads to increase in the sub threshold leakage current and hence static power dissipation. Although power consumption is important for modern VLSI design, the main requirements of the VLSI design are, operating speed and occupied area. Multithreshold voltage CMOS (MTCMOS) technology is a good solution providing high speed performance and low power design without area overhead. MTCMOS technology provides the transistors that have low, high and normal threshold voltage. The low threshold voltage transistors are used to reduce the propagation delay in critical (longest) path, the high-threshold voltage transistors are used to reduce the power consumption in shortest path. This paper describes a high-speed performance and low-power consumption design for full adder (using 2 half-adder), 4-bit ripple carry adder, 4x4 multiplier and 16-bit carry look-ahead adder circuits with MTCMOS technology using 45nm technology.

Keywords: Multi-threshold voltage CMOS (MTCMOS), static power consumption, propagation delay, sub threshold current.

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DOI: 01.1617/vol3iss5pid306

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,

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ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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Journal Code : IJERECE
Electronic ISSN : 2394-6849
Impact Factor : 3.689
Frequency : monthly
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