Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Reference :

  1. [1] B. J. Sheu, D. L. Scharfetter, P. K. Ko, and M. C. Jeng, “BSIM: Berkeleyshort channel IGFET model for MOS transistors,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 558–566, Aug. 1987.

    [2] S. Thompson, P. Packan, and M. Bohr, “MOS scaling: Transistor challenges for the 21st century,” Intel Technol. J., vol. Q3, 1998.

    [3] Dong Whee Kim, Jeong Beom Kee, “Low-Power Carry Look- Ahead Adder With Multi-Threshold Voltage CMOS Technology”, in Proceeding of ICSICT International Conference on Solid-State and Integrated-Circuit Technology, pp. 2160- 2163, 2008.

    [4] L.Wei, Z. Chen, M. Johnson, K. Roy, Y. Ye, and V. De, “Design and optimization of dual threshold circuits for low voltage low power applications,” IEEE Trans. VLSI Systems, pp. 16–24, Mar. 1999.

    [5] P. Pant, V. K. De, and A. Chatterjee, “Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits,” IEEE Trans. VLSI Syst., vol. 6, pp. 538–545, Dec. 1998.

    [6] Q. Wang and S. Vrudhula, “Static power optimization of deep submicron CMOS circuits for dual Vt technology,” in Proc. ICCAD, Apr. 1998, pp. 490–496

    [7] H. J. M Veendrick, “Short circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits ,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 468–473, Aug. 1984.

    [8] A. P. Chandrakasan and R. W. bBrodersen, “Minimizing power consumption in digital CMOS circuits,” Proc. IEEE, vol. 83, pp. 498–523, Apr. 1995.

    [9] R. X. Gu and M. I. Elmasry, “Power dissipation analysis and op-timization for deep submicron CMOSdigital circuits,” IEEE J. Solid-State Circuits, vol. 31, pp. 707–713, May 1999.

    [10] J. Kao, A. Chandrakasan, and D. Antoniadis, “Transistor sizing issues and tool for multi-threshold CMOS technology,” in Proc. 34th DAC, 1997, pp. 409– 414.

    [11] L. Wei, Z. Chen, M. Johnson, and K. Roy, “Design and optmization of low voltage high performance dual threshold CMOS circuits,” in Proc. 35th DAC, 1998, pp. 489–492.

    [12] Nirmal U.,Sharma G.,Mishra Y., “Low Power Full Adder Using MTCMOS Technique”in proceeding of International Conference on Advances in Information, Communication Technology and VLSI Design, Coimbatore, India, August 2010.

    [13] Nirmal U.,Sharma G.,Mishra Y.,“ MTCMOS technique to minimize stand-by leakage power in nanoscale CMOS VLSI”, in proceeding of International Conference on System Dynamics and Control,Manipal, India, August 2010.


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