International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,May 2016,

Topic : FPGA Implementation of Reconfigurable Pulse-Shaping FIR Interpolation Filter with Carry Select Adder

Authors:Devikarani H S || Lakshmi Shrinivasan

Abstract:This paper proposes the Field Programmable Gate Array (FPGA) architecture implementation of reconfigurable RootRaised Cosine (RRC), Finite Impulse Response (FIR) filter in which all the adders present in the designed filter are replaced by the modified Carry-Select Adders (CSLA), which is mostly used in Digital Up Converter (DUC). The proposed filter can be reconfigured with one of three different interpolation factors of 4, 6, and 8 for 25, 37, and 49-taps filters respectively and one of two roll-off factors. The basic element of a filter is multiplier and 2-bit Binary Common Sub expression Elimination (BCSE) algorithm is used in the design of the multiplier in this work. It is a two-step optimization technique of designing a reconfigurable VLSI architecture of interpolation filter to reduce the number of slices required for the filter. The maximum operating frequency analysis is carried out using Xilinx Synthesis Tool (XST) and Cadence software..

Keywords: BCSE, Cadence, CSLA, DUC, FIR, Interpolation factor, Roll-off factor, RRC, VLSI, XST.

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DOI: 01.1617/vol3iss5pid310


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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