Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Reference :

  1. [1] Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee,”Reconfigurable Architecture Of A RRC FIR Interpolator For Multistandard Digital Up Converter”, 2013 IEEE 27th International Symposium on Parallel Distributed Processing Workshops and PhD Forum.

    [2] Indranil Hatai, Indrajit Chakrabarti, and Swapna Banerjee,”An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC”, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 6, June 2015.

    [3] R. Mahesh and A. P. Vinod,”A New Common Subexpression Elimination Algorithm For Implementing Low Complexity FIR Fillters in Sofware Defined Radio Receivers”, 0-7803-9390- 2/06, 2006 IEEE.

    [4] A.P Vinod and E.M-K Lai,”Comparison of the horizontal and the vertical common subexpression elimination methods for realizing digital filters”, Proceedings of IEEE International Conference on the Circuits and Systems, 2005, pp.496-499.

    [5] Indranil Hatai, Indrajit Chakrabarti,and Swapna Banerjee,”An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Subexpression Elimination Algorithm for Reconfigurable FIR Filter Synthesis”, ”, IEEE Transactions On Circuits And Systems-2015.

    [6] S. F. Lin, S. C. Huang, F. S. Yang, C. W. Ku, and L. G. Chen,”Powerefficient FIR filter architecture design for wireless embedded system”, IEEE Trans. Circuits System II, Exp. Briefs, vol. 51, no. 1, pp. 21–25, Jan-2004.

    [7] K. H. Chen and T. D. Chieueh,”A low-power digitbased reconfigurable FIR filter”, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 617–621, Aug2006.

    [8] R. Mahesh and A. P. Vinod,”A new common Subexpression elimination algorithm for realizing lowcomplexity higher order digital filters”, IEEE Trans. Computer-Aided Design Integr. Circuits Systems, vol. 27, no. 2, pp. 217–229, Feb-2008.

    [9] R. Mahesh and A. P. Vinod,”New reconfigurable architectures for implementing FIR filters with low complexity”, IEEE Trans. Computer Aided Design Integr. Circuits Systems, vol. 29, no. 2, pp. 275–288, Feb-2010

    [10] B. Ramkumar and Harish M Kittur,”Low- Power And Area-Efficient Carry Select Adder”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 2, Feb-2012


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