International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,May 2016,

Topic : Design and Implementation of 4x4 Pipelined Iterative Logarithmic Multiplier using Reversible Logic

Authors:Kavya Shree M S || Praveen Kumar Y G , Dr. M Z Kurian

Abstract:As the demand increases for low power dissipation in digital computing system, a new technique called Reversible Logic was introduced. Reversible logic is one of the promising field which solves the problem of power dissipation and also it is the basic requirement for the field of quantum computing. The multiplication which plays a prior role in DSP applications. Some of the important operations in DSP are filtering, convolution and inner partial products. These are the processes which requires multipliers so the speed and performance of their operations depends on the speed of the multiplication and addition. The logarithmic multiplier which is designed based on the Mitchell’s Algorithm proposed by Mitchell. The logarithmic multiplier convert multiplication and division problem into addition and subtraction.. This paper gives the design of pipelined iterative logarithmic multiplier using reversible logic..

Keywords: Reversible Logic, quantum Computing, Logarithmic Multiplier, Mitchell’s Algorithm.

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DOI: 01.1617/vol3iss5pid319


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
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