International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,May 2016,

Topic : FPGA Implementation of High Throughput Dual Key based AES Encryption and Decryption

Authors:Naveen Kumar M S || Manjunath C Lakhannavar

Abstract:Data security plays a major role in today’s technology. Cryptography is one of the industry standards in providing data security since many years. Federal Information Processing Standard (FIPS) is approved Advance Encryption Standard (AES) cryptographic algorithm that can be used to protect electronic data. But the conventional scheme of AES is vulnerable for cryptanalysis, due to static S-box which will never vary with the input text/key. Noticeable drawbacks with AES are, it can only support one key, and is prone to easy reverse engineering which can lead to insecure data. Thus S-box value is necessary for changes in input key. In this paper, a new scheme of AES is discussed which involves in the generation of Key based S-Boxes, with dual key AES and implemented in pipeline architecture to improve the throughput with low latency..

Keywords: AES, Encryption, Decryption, S-Box, Dual key, Pipeline, Cryptography, Security

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DOI: 01.1617/vol3iss5pid328


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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