International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,June 2016,

Topic : An Efficient Design of Dynamic VITERBI Decoder Architecture

Authors:Mr.Parsekar Gaurav Rajanikant || Mrs.Veena H.S , Mr.Girish G Satardekar

Abstract:The emerging applications of wireless networks enforce new challenges in design of algorithms and communication protocols. In such scenario of challenges, coding for error control has be- come extremely important to provide robust communication and maintain quality of service. One method to improve Bit Error Rate (BER) while maintaining high data reliability, is to use an error correction technique like the VITERBI algorithm. The VITERBI algorithm provides an efficient method for Forward Error Correction (FEC) that improves channel reliability. As constraint length associated with input bits increases it needs to implement it with lesser computations and lesser hardware to decode the original data. Therefore Dynamic VITERBI Algorithm is used for decoding which reduces error probability, computation and employ lesser hard- ware with increased speed. The purpose of this paper is to understand VITERBI Algorithm, Adaptive VITERBI Algorithm and to find the alternative to shortcomings in the design and implement the idea on a hardware..

Keywords: Dynamic VITERBI decoder, constraint length, Adaptive VITERBI decoder, forward error correcting codes.

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DOI: 01.1617/vol3iss6pid359


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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