International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume3,August 2016,

Topic : Design of Sequential Adder by Using Multi Bit Flip-flop for Power Reduction Technique

Authors:G. Sravani ||

Abstract:In VLSI design the power consumption is increased for more transition memory elements. Flip-flop (FF) are the basic sequential components used for memory applications. An adder and multiplier are designed using Multi-Bit Flip-Flop (MBFF). In the proposed work one of the promising ways to improve performance of FF is merging of clock pulse. Operating memory arrays with less clock cycle will reduce the power taken by the FF which leads to total power reduction and maximum internal delay can also be reduced. Besides, reducing number of FF in the circuit design the total wire length reduces the complexity of MBFF. For dynamic storage the required number of FF selected by transformation check method. Transformation check method can be effectively enabled by dynamic combinational block with check task in the proposed work.

Keywords: Power reduction, MBFF, Merging, Synthesis for low power, Wire length, Transformation check method.

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DOI: 01.1617/vol3iss8pid418


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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